1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a circuit configuration that suppresses the influence of the process variation of wire resistance on characteristics of the semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor integrated circuits which can decrease the variation of bias currents among chips to reduce the difference of current consumption among the chips and the difference of device characteristics are known in the art. Japanese Patent Application Laid-Open (Kokai) No. 2000-310981 (paragraph 0089), for example, discloses that the same bias current is supplied to each chip from the outside in order to suppress the current consumption difference and characteristic difference among different chips. The bias current is used to decide a current to flow in amplifiers of each chip. A bias generation circuit, which determines the bias current, is installed outside the chip, so that this circuit supplies the same bias current to each chip.
Japanese Patent Application Laid-Open No. 2000-310981 discloses a technology for installing the bias generation circuit outside the chip, and not for decreasing the variation of bias currents among a plurality of amplifier circuits, and decreasing the difference of current consumption and difference of device characteristics by deciding appropriate positions of the amplifier circuits and the bias generation circuit on a same chip. This Japanese Patent Application Laid-Open No. 2000-310981 does not provide a useful technology for suppressing the influence of process variation of the wiring resistance on characteristics of the products, because chips become long, such as the case of a semiconductor integrated circuit device used for a liquid crystal TFT driver, and power supply and ground wires from the power supply and ground supply terminals to the internal circuits become long.